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IS42S16400F IS45S16400F
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
* Clock frequency: 200, 166, 143, 133 MHz * Fullysynchronous;allsignalsreferencedtoa positive clock edge * Internalbankforhidingrowaccess/precharge * Single3.3Vpowersupply * LVTTLinterface * Programmableburstlength - (1, 2, 4, 8, full page) * Programmableburstsequence: Sequential/Interleave * Selfrefreshmodes * Autorefresh(CBR) * 4096refreshcyclesevery64ms(Com,Ind,A1 grade) or 16ms (A2 grade) * Randomcolumnaddresseveryclockcycle * ProgrammableCAS latency (2, 3 clocks) * Burstread/writeandburstread/singlewrite operations capability * Burstterminationbyburststopandprecharge command OPTIONS * Package: 54-pinTSOPII 54-ballFBGA(8mmx8mm) * OperatingTemperatureRange Commercial (0oC to +70oC) Industrial (-40oC to +85oC) AutomotiveGradeA1(-40oC to +85oC) AutomotiveGradeA2(-40oC to +105oC) NOVEMBER 2009
OVERVIEW ISSI's64MbSynchronousDRAMisorganizedas1,048,576
bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter ClkCycleTime CASLatency=3 CASLatency=2 ClkFrequency CASLatency=3 CASLatency=2 AccessTimefromClock CASLatency=3 CASLatency=2 -5 5 7.5 200 133 5 6 -6 6 7.5 166 133 5.4 6 -7 7 7.5 143 133 5.4 6 Unit ns ns Mhz Mhz ns ns
ADDRESS TABLE
Parameter Configuration Refresh Count 4M x 16 1M x 16 x 4 banks Com./Ind. 4K/64ms A1 4K/64ms A2 4K/16ms A0-A11 A0-A7 BA0, BA1 A10/AP
Row Addresses Column Addresses Bank Address Pins Auto Precharge Pins
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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Rev. F 11/09/09
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GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The64MbSDRAMincludesanAUTOREFRESHMODE, and a power-saving, power-down mode. All signals are registeredonthepositiveedgeoftheclocksignal,CLK. AllinputsandoutputsareLVTTLcompatible. The64MbSDRAMhastheabilitytosynchronouslyburst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1selectthebank;A0-A11selecttherow).TheREAD or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. ProgrammableREADorWRITEburstlengthsconsistof 1, 2, 4 and 8 locations, or full page, with a burst terminate option.
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE A10
DQM COMMAND DECODER & CLOCK GENERATOR
DATA IN BUFFER
16 16
MODE REGISTER
12
REFRESH CONTROLLER
DQ 0-15
SELF REFRESH CONTROLLER
A11
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
12
16
DATA OUT BUFFER
VDD/VDDQ GND/GNDQ
16
REFRESH COUNTER
4096 4096 4096 4096
ROW DECODER
MULTIPLEXER
12
MEMORY CELL ARRAY
ROW ADDRESS LATCH
12
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
8
256K (x 16)
BANK CONTROL LOGIC
BURST COUNTER COLUMN ADDRESS BUFFER
COLUMN DECODER
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PIN CONFIGURATION PACKAge Code: B 54 BALL fBgA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
123456789 A B C D E F G H J
GND DQ15 GNDQ DQ14 DQ13 VDDQ DQ12 DQ11 GNDQ DQ10 DQ9 VDDQ DQ8 NC GND CKE A9 A6 A4 VDDQ DQ0 GNDQ DQ2 VDDQ DQ4 GNDQ DQ6 VDD DQ1 DQ3 DQ5
VDD DQML DQ7 CAS BA0 A0 A3 RAS BA1 A1 A2 WE CS A10 VDD
DQMH CLK NC A8 GND A11 A7 A5
PIN DESCRIPTIONS
A0-A11 A0-A7 BA0, BA1 dQ0 to dQ15 CLK CKe CS RAS CAS Row Address Input Column Address Input Bank Select Addresses data I/o System Clock Input Clock enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LdQM, UdQM Vdd gNd Vddq gNdQ NC Write enable x16 Input/output Mask Power ground Power Supply for I/o Pin ground for I/o Pin No Connection
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PIN CONFIGURATIONS
54 pin TSOP - Type II
VDD DQ0 VDDQ DQ1 DQ2 GNDQ DQ3 DQ4 VDDQ DQ5 DQ6 GNDQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
GND DQ15 GNDQ DQ14 DQ13 VDDQ DQ12 DQ11 GNDQ DQ10 DQ9 VDDQ DQ8 GND NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A11 A0-A7 BA0,BA1 DQ0toDQ15 CLK CKE CS RAS CAS RowAddressInput Column Address Input BankSelectAddress DataI/O SystemClockInput ClockEnable Chip Select RowAddressStrobeCommand Column Address Strobe Command WE LDQM UDQM Vdd GND Vddq GNDq NC WriteEnable x16LowerByte,Input/OutputMask x16UpperByte,Input/OutputMask Power Ground PowerSupplyforI/OPin GroundforI/OPin NoConnection
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PIN FUNCTIONS
Symbol A0-A11 TSOP Pin No. 23to26 29 to 34 22, 35 Type InputPin Function (In Detail) AddressInputs:A0-A11aresampledduringtheACTIVE command(row-addressA0-A11)andREAD/WRITEcommand(A0-A7 with A10 defining auto precharge) to select one location out of the memory array intherespectivebank.A10issampledduringaPRECHARGEcommandtodetermineifallbanksaretobeprecharged(A10HIGH)orbankselectedby BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOAD MODEREGISTERcommand. BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE,READ,WRITE orPRECHARGEcommandisbeingapplied. CAS, in conjunction with the RAS and WE, forms the device command. See the "CommandTruthTable"fordetailsondevicecommands. TheCKEinputdetermineswhethertheCLKinputisenabled.Thenextrisingedge oftheCLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW.WhenCKE isLOW,thedevicewillbeineitherpower-downmode,clocksuspendmode,orself refresh mode. CKEisan asynchronous input. CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdevice are acquired in synchronization with the rising edge of this pin. TheCS input determines whether command input is enabled within the device. Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.The device remains in the previous state when CSisHIGH. DQ0toDQ15areI/Opins.I/Othroughthesepinscanbecontrolledinbyteunits usingtheLDQMandUDQMpins. LDQMandUDQMcontrolthelowerandupperbytesoftheI/Obuffers.Inread mode,LDQMandUDQMcontroltheoutputbuffer.WhenLDQMorUDQMisLOW, thecorrespondingbufferbyteisenabled,andwhenHIGH,disabled.Theoutputs gototheHIGHimpedancestatewhenLDQM/UDQMisHIGH.Thisfunctioncorresponds to OEinconventionalDRAMs.Inwritemode,LDQMandUDQMcontrol theinputbuffer.WhenLDQMorUDQMisLOW,thecorrespondingbufferbyteisenabled,anddatacanbewrittentothedevice.WhenLDQMorUDQMisHIGH,input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. WE, in conjunction with RAS and CAS, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. Vddq is the output buffer power supply. Vdd is the device internal power supply. GNdq is the output buffer ground. GNd is the device internal ground.
BA0,BA1 CAS CKE
20,21 17 37
InputPin InputPin InputPin
CLK CS
38 19
InputPin InputPin
DQ0 to DQ15 LDQM, UDQM
2,4,5,7,8,10, 11,13, 42, 44, 45, 47, 48, 50, 51, 53 15,39
DQPin InputPin
RAS WE Vddq Vdd GNdq GNd
18 16 3,9,43,49 1,14,27 6,12,46,52 28,41,54
InputPin InputPin PowerSupplyPin PowerSupplyPin PowerSupplyPin PowerSupplyPin
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READ
TheREADcommandselectsthebankfromBA0,BA1inputs and starts a burst read access to an active row. Inputs A0-A7providesthestartingcolumnlocation.WhenA10is HIGH,thiscommandfunctionsasanAUTOPRECHARGE command.Whentheautoprechargeisselected,therow beingaccessedwillbeprechargedattheendoftheREAD burst.Therowwillremainopenforsubsequentaccesses when AUTO PRECHARGE is not selected. DQ's read data is subject to the logic level on the DQM inputs two clocksearlier.WhenagivenDQMsignalwasregistered HIGH,thecorrespondingDQ'swillbeHigh-Ztwoclocks later.DQ'swillprovidevaliddatawhentheDQMsignal wasregisteredLOW. eitherenabledordisabled.AUTOPRECHARGEdoesnot applyexceptinfull-pageburstmode.Uponcompletionof theREADorWRITEburst,aprechargeofthebank/row that is addressed is automatically performed.
AUTO REFRESH COMMAND
ThiscommandexecutestheAUTOREFRESHoperation. Therowaddressandbanktoberefreshedareautomatically generatedduringthisoperation. Thestipulatedperiod(trc) is required for a single refresh operation, and no other commandscanbeexecutedduringthisperiod. Thiscommand isexecutedatleast4096timeseveryTref.DuringanAUTO REFRESHcommand,addressbitsare"Don'tCare".This commandcorrespondstoCBRAuto-refresh.
WRITE
A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7.Whether or not AUTO-PRECHARGE is used is determined by A10. Therowbeingaccessedwillbeprechargedattheendof theWRITE burst, if AUTO PRECHARGE is selected. If AUTOPRECHARGEisnotselected,therowwillremain open for subsequent accesses. A memory array is written with corresponding input data onDQ'sandDQMinputlogiclevelappearingatthesame time. Data will be written to memory when DQM signal is LOW.WhenDQMisHIGH,thecorrespondingdatainputs willbeignored,andaWRITEwillnotbeexecutedtothat byte/column location.
SELF REFRESH
DuringtheSELFREFRESHoperation,therowaddressto be refreshed, the bank, and the refresh interval are generatedautomaticallyinternally.SELFREFRESHcanbe usedtoretaindataintheSDRAMwithoutexternalclocking, eveniftherestofthesystemispowereddown.TheSELF REFRESHoperationisstartedbydroppingtheCKEpin fromHIGHtoLOW.DuringtheSELFREFRESHoperation allotherinputstotheSDRAMbecome"Don'tCare".The device must remain in self refresh mode for a minimum period equal to tras or may remain in self refresh mode foranindefiniteperiodbeyondthat.TheSELF-REFRESH operationcontinuesaslongastheCKEpinremainsLOW andthereisnoneedforexternalcontrolofanyotherpins. Thenextcommandcannotbeexecuteduntilthedevice internal recovery period (trc) has elapsed. Once CKE goesHIGH,theNOPcommandmustbeissued(minimum of two clocks) to provide time for the completion of any internal refresh in progress. After the self-refresh, since it is impossible to determine the address of the last row to berefreshed,anAUTO-REFRESHshouldimmediatelybe performed for all addresses.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0,BA1canbeusedtoselectwhichbankisprecharged or they are treated as "Don't Care". A10 determines whether one or all banks are precharged. After executing this command, the next command for the selected bank(s)isexecutedafterpassageoftheperiodtRP, which istheperiodrequiredforbankprecharging.Onceabank has been precharged, it is in the idle state and must be activatedpriortoanyREADorWRITEcommandsbeing issued to that bank.
BURST TERMINATE
The BURSTTERMINATE command forcibly terminates the burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registeredREADorWRITEcommandpriortotheBURST TERMINATE.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst.Thisfunctionallowsforindividual-bankprecharge withoutrequiringanexplicitcommand.A10canbeused toenabletheAUTOPRECHARGEfunctioninconjunctionwithaspecificREADorWRITEcommand.Foreach individualREADorWRITEcommand,autoprechargeis 6
COMMAND INHIBIT
COMMANDINHIBITpreventsnewcommandsfrombeing executed.Operationsinprogressarenotaffected,apart fromwhethertheCLKsignalisenabled
NO OPERATION
WhenCSislow,theNOPcommandpreventsunwanted commands from being registered during idle or wait states. Integrated Silicon Solution, Inc. -- www.issi.com
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LOAD MODE REGISTER
DuringtheLOADMODEREGISTERcommandthemode registerisloadedfromA0-A11.Thiscommandcanonly be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputsonA0-A11selectstherow.UntilaPRECHARGE command is issued to the bank, the row remains open for accesses.
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TRUTH TABLE - COMMANDS AND DQM OPERATION(1)
FUNCTION CS COMMANDINHIBIT(NOP) H NOOPERATION(NOP) L (3) ACTIVE(Selectbankandactivaterow) L (4) READ(Selectbank/column,startREADburst) L WRITE(Selectbank/column,startWRITEburst)(4) L BURSTTERMINATE L (5) PRECHARGE(Deactivaterowinbankorbanks) L AUTOREFRESHorSELFREFRESH(6,7) L (Enter self refresh mode) LOADMODEREGISTER(2) L (8) WriteEnable/OutputEnable -- (8) WriteInhibit/OutputHigh-Z -- RAS X H L H H H L L L -- -- CAS X H H L L H H L L -- -- WE X H H H L L L H L -- -- DQM X X X L/H(8) L/H(8) X X X X L H ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code -- -- DQs X X X X Valid Active X X X Active High-Z
NOTES: 1. CKEisHIGHforallcommandsexceptSELFREFRESH. 2. A0-A11 define the op-code written to the mode register. 3. A0-A11providerowaddress,andBA0,BA1determinewhichbankismadeactive. 4. A0-A7(x16)providecolumnaddress;A10HIGHenablestheautoprechargefeature(nonpersistent),whileA10LOWdisables autoprecharge;BA0,BA1determinewhichbankisbeingreadfromorwrittento. 5. A10LOW:BA0,BA1determinethebankbeingprecharged.A10HIGH:AllbanksprechargedandBA0,BA1are"Don'tCare." 6. AUTOREFRESHifCKEisHIGH,SELFREFRESHifCKEisLOW. 7. Internalrefreshcountercontrolsrowaddressing;allinputsandI/Osare"Don'tCare"exceptforCKE. 8. ActivatesordeactivatestheDQsduringWRITEs(zero-clockdelay)andREADs(two-clockdelay).
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TRUTH TABLE - CKE (1-4)
CURRENT STATE Power-Down SelfRefresh ClockSuspend Power-Down(5) SelfRefresh(6) Clock Suspend(7) AllBanksIdle AllBanksIdle ReadingorWriting COMMANDn X X X COMMANDINHIBITorNOP COMMANDINHIBITorNOP X COMMANDINHIBITorNOP AUTOREFRESH VALID ACTIONn MaintainPower-Down MaintainSelfRefresh MaintainClockSuspend ExitPower-Down ExitSelfRefresh ExitClockSuspend Power-DownEntry SelfRefreshEntry ClockSuspendEntry CKEn-1 L L L L L L H H H H CKEn L L L H H H L L L H
See TRUTH TABLE - CURRENT STATE BANK n, COMMAND TO BANK n
NOTES: 1. CKEnisthelogicstateofCKEatclockedgen;CKEn-1 wasthestateofCKEatthepreviousclockedge. 2. CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen. 3. COMMANDnisthecommandregisteredatclockedgen,andACTONnisaresultofCOMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exitingpower-downatclockedgen will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is met). 6. Exitingselfrefreshatclockedgen will put the device in all banks idle state once txsrismet.COMMANDINHIBITorNOP commands should be issued on clock edges occurring during the txsrperiod.AminimumoftwoNOPcommandsmustbesent during txsr period. 7. Afterexitingclocksuspendatclockedgen,thedevicewillresumeoperationandrecognizethenextcommandatclockedge n+1.
TRUTH TABLE - CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENTSTATE Any Idle RowActive Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) COMMAND(ACTION) COMMANDINHIBIT(NOP/Continuepreviousoperation) NOOPERATION(NOP/Continuepreviousoperation) ACTIVE(Selectandactivaterow) AUTOREFRESH(7) LOADMODEREGISTER(7) PRECHARGE(11) READ(SelectcolumnandstartREADburst)(10) WRITE(SelectcolumnandstartWRITEburst)(10) PRECHARGE(Deactivaterowinbankorbanks)(8) READ(SelectcolumnandstartnewREADburst)(10) WRITE(SelectcolumnandstartWRITEburst)(10) PRECHARGE(TruncateREADburst,startPRECHARGE)(8) BURSTTERMINATE(9) READ(SelectcolumnandstartREADburst)(10) WRITE(SelectcolumnandstartnewWRITEburst)(10) PRECHARGE(TruncateWRITEburst,startPRECHARGE)(8) BURSTTERMINATE(9) CS RAS CAS WE H X X X L H H H L L H H L L L H L L L L L L H L L H L H L H L L L L H L L H L H L H L L L L H L L H H L L H L H L H L L L L H L L H H L
NOTE: 1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(seeTruthTable-CKE)andaftertxsr has been met (if the previous state was SELFREFRESH). 2.Thistableisbank-specific,exceptwherenoted;i.e.,thecurrentstateisforaspecificbankandthecommandsshownarethose allowedtobeissuedtothatbankwheninthatstate.Exceptionsarecoveredinthenotesbelow.
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3. Current state definitions: Idle:Thebankhasbeenprecharged,andtrp has been met. RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister accesses are in progress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. 4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.COMMANDINHIBITorNOPcommands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commandstotheotherbankaredeterminedbyitscurrentstateandCURRENTSTATEBANKntruthtables. Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentrpismet.Oncetrp is met, the bank will be in the idle state. RowActivating:StartswithregistrationofanACTIVEcommandandendswhentrcdismet.Oncetrcd is met, the bank will be in the row active state. Readw/Auto PrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. Writew/Auto PrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. 5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;COMMANDINHIBITorNOPcommandsmustbe applied on each positive clock edge during these states. Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentrcismet.Oncetrc is met, the SDRAMwillbeintheallbanksidlestate. Accessing Mode Register:StartswithregistrationofaLOADMODEREGISTERcommandandendswhentmrdhasbeenmet.Once tmrdismet,theSDRAMwillbeintheallbanksidlestate. PrechargingAll:StartswithregistrationofaPRECHARGEALLcommandandendswhentrpismet.Oncetrp is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7.Notbank-specific;requiresthatallbanksareidle. 8.Mayormaynotbebank-specific;ifallbanksaretobeprecharged,allmustbeinavalidstateforprecharging. 9.Notbank-specific;BURSTTERMINATEaffectsthemostrecentREADorWRITEburst,regardlessofbank. 10.READsorWRITEslistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabledand READsorWRITEswithautoprechargedisabled. 11.DoesnotaffectthestateofthebankandactsasaNOPtothatbank.

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TRUTH TABLE - CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENTSTATE Any Idle Row Activating, Active,or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (WithAuto Precharge) Write (WithAuto Precharge) COMMAND(ACTION) COMMANDINHIBIT(NOP/Continuepreviousoperation) NOOPERATION(NOP/Continuepreviousoperation) AnyCommandOtherwiseAllowedtoBankm ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartREADburst)(7) WRITE(SelectcolumnandstartWRITEburst)(7) PRECHARGE ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartnewREADburst)(7,10) WRITE(SelectcolumnandstartWRITEburst)(7,11) PRECHARGE(9) ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartREADburst)(7,12) WRITE(SelectcolumnandstartnewWRITEburst) (9) PRECHARGE ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartnewREADburst)(7,8,14) WRITE(SelectcolumnandstartWRITEburst)(7,8,15) PRECHARGE(9) ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartREADburst)(7,8,16) WRITE(SelectcolumnandstartnewWRITEburst)(7,8,17) PRECHARGE(9)
(7,13)
CS RAS CAS WE H X X X L H H H X X X X L L H H L H L H L H L L L L H L L L H H L H L H L H L L L L H L L L H H L L L L L L L L L L L H H L L H H L L H H L L L H H L L H H L L H H L L H H L L H H L L
NOTE: 1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(TruthTable-CKE)andaftertxsr has been met (if the previous state was self refresh). 2.Thistabledescribesalternatebankoperation,exceptwherenoted;i.e.,thecurrentstateisforbankn and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable).Exceptions are covered in the notes below. 3. Current state definitions: Idle:Thebankhasbeenprecharged,andtrp has been met. RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister accesses are in progress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. Readw/Auto PrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabled,andendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. Writew/Auto PrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabled,andendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. 4.AUTOREFRESH,SELFREFRESHandLOADMODEREGISTERcommandsmayonlybeissuedwhenallbanksareidle. 5.ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstate only. 6. All states and sequences not shown are illegal or reserved. 7.READsorWRITEstobankmlistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabled andREADsorWRITEswithautoprechargedisabled.
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8.CONCURRENTAUTOPRECHARGE:BanknwillinitiatetheAUTOPRECHARGEcommandwhenitsbursthasbeeninterruptedbybankm'sburst. 9.Burstinbankncontinuesasinitiated. 10.ForaREADwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt theREADonbankn,CASlatencylater(ConsecutiveREADBursts). 11.ForaREADwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupttheREADonbanknwhenregistered(READtoWRITE).DQMshouldbeusedoneclockpriortotheWRITEcommandto prevent bus contention. 12.ForaWRITEwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt theWRITEonbanknwhenregistered(WRITEtoREAD),withthedata-outappearingCASlatencylater.ThelastvalidWRITE tobanknwillbedata-inregisteredoneclockpriortotheREADtobankm. 13.ForaWRITEwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupttheWRITEonbanknwhenregistered(WRITEtoWRITE).ThelastvalidWRITEtobanknwillbedata-inregisteredone clockpriortotheREADtobankm. 14.ForaREADwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterruptthe READonbankn,CASlatencylater.ThePRECHARGEtobanknwillbeginwhentheREADtobankmisregistered(FigCAP 1). 15.ForaREADwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt theREADonbanknwhenregistered.DQMshouldbeusedtwoclockspriortotheWRITEcommandtopreventbuscontention. ThePRECHARGEtobanknwillbeginwhentheWRITEtobankmisregistered(FigCAP2). 16.ForaWRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt theWRITEonbanknwhenregistered,withthedata-outappearingCASlatencylater.ThePRECHARGEtobanknwillbegin after tWR is met, where twrbeginswhentheREADtobankmisregistered.ThelastvalidWRITEtobanknwillbedata-inregisteredoneclockpriortotheREADtobankm(FigCAP3). 17.ForaWRITEwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt theWRITEonbanknwhenregistered.ThePRECHARGEtobanknwillbeginaftertwrismet,wheretWRbeginswhenthe WRITEtobankmisregistered.ThelastvalidWRITEtobanknwillbedataregisteredoneclockpriortotheWRITEtobankm (FigCAP4).
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Vdd max Vddq max ViN Vout Pd max Ics Topr Parameters MaximumSupplyVoltage MaximumSupplyVoltageforOutputBuffer InputVoltage OutputVoltage AllowablePowerDissipation output Shorted Current operatingTemperature Com. Ind. A1 A2 StorageTemperature Rating -1.0to+4.6 -1.0to+4.6 -1.0toVddq +0.5 -1.0toVddq +0.5 1 50 0 to +70 -40 to +85 -40 to +85 -40 to +105 -65to+150 Unit V V V V W mA C C C C C
Tstg
DC RECOMMENDED OPERATING CONDITIONS(2) (AtTa=0to+70Cforcommercialgrade.Ta=-40to+85CforindustrialandA1grade.Ta=-40to+105CforA2grade)
Symbol Vdd, Vddq Vih Vil Parameter SupplyVoltage InputHighVoltage(3) InputLowVoltage(4) Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- Max. 3.6 Vdd +0.3 +0.8 Unit V V V
CAPACITANCE CHARACTERISTICS(1,2) (AtTa=0to+25C,Vdd=Vddq=3.30.3V,f=1MHz)
Symbol CiN Cclk CI/O Parameter InputCapacitance:AddressandControl InputCapacitance:(CLK) DataInput/OutputCapacitance:I/O0-I/O15 Typ. -- -- -- Max. 3.8 3.5 6.5 Unit pF pF pF
Notes: 1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffect reliability. 2. AllvoltagesarereferencedtoGND. 3.Vih(max)=Vddq+1.2Vwithapulsewidth<3ns. 4.Vil(min)=GND-1.2Vwithapulsewidth<3ns.
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DC ELECTRICAL CHARACTERISTICS (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol iil iol Voh Vol icc1 Parameter InputLeakageCurrent OutputLeakageCurrent OutputHighVoltageLevel OutputLowVoltageLevel OperatingCurrent(1,2) Test Condition Speed 0VViN Vdd, with pins other than thetestedpinat0V Outputisdisabled,0V Vout Vdd iout=-2mA iout=+2mA OneBankOperation, CASlatency=3 Com. -5 BurstLength=1 Com. -6 trc trc (min.) Com. -7 Iout=0mA A1,Ind. -6 A1, A2, Ind. -7 CKE Vil (max) tck=15ns Com. -- A1, A2, Ind. -- tck = Com. -- A1, A2, Ind. -- CKE Vih (miN) tck=15ns -- tck = Com. -- A1, A2, Ind. -- CKE Vil (max) tck=15ns Com. -- A1, A2, Ind. -- tck = Com. -- A1, A2, Ind. -- CKE Vih (miN) tck=15ns -- tck = Com. -- A1, A2, Ind. -- tck=tck (miN) CASlatency=3 Com. -5 Iout =0mA Com. -6 BL=4;4banksactivated Com. -7 A1, Ind. -6 A1, A2, Ind. -7 trc=trc (miN) CASlatency=3 Com. -5 tclk=tclk (miN) Com. -6 Com. -7 A1, Ind. -6 A1, A2, Ind. -7 CKE0.2V -- Min. -5 -5 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5 5 -- 0.4 110 95 85 155 145 2 4 2 3 20 15 15 7 7 5 5 30 25 25 140 130 100 140 110 160 150 130 170 150 2 Unit A A V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
icc2p Icc2ps icc2N(3) Icc2Ns icc3p icc3ps icc3N(3) Icc3Ns icc4
PrechargeStandbyCurrent (InPower-DownMode) PrechargeStandbyCurrent (InNonPower-DownMode) ActiveStandbyCurrent (InPower-DownMode) ActiveStandbyCurrent (InNonPower-DownMode) OperatingCurrent (InBurstMode)(1)
icc5
Auto-RefreshCurrent
icc6
Self-RefreshCurrent
Notes: 1. Thesearethevaluesattheminimumcycletime.Sincethecurrentsaretransient,thesevaluesdecreaseasthecycletimeincreases.Alsonotethatabypasscapacitorofatleast0.01FshouldbeinsertedbetweenVddandGNDforeachmemorychip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4dependontheoutputload.ThemaximumvaluesforIcc1 and Icc4 are obtained with the output open state. 3. Input signal chnage once per 30ns.
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AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5 Symbol tck3 tck2 tac3 tac2 tchi tcl toh3 toh2 tlz thz3 thz2 tds tdh tas tah tcks tckh tcka tcs tch trc tras trp trcd trrd tdpl or twr tdal tt txsr tref CASLatency=3 CASLatency=2 (4,6) AccessTimeFromCLK CASLatency=3 CASLatency=2 CLKHIGHLevelWidth CLKLOWLevelWidth (6) OutputDataHoldTime CASLatency=3 CAS Latency=2 OutputLOWImpedanceTime (5) OutputHIGHImpedanceTime CASLatency=3 CASLatency=2 InputDataSetupTime InputDataHoldTime AddressSetupTime AddressHoldTime CKESetupTime CKEHoldTime CKEtoCLKRecoveryDelayTime CommandSetupTime(CS, RAS, CAS, WE, DQM) CommandHoldTime(CS, RAS, CAS, WE, DQM) CommandPeriod(REFtoREF/ACTtoACT) CommandPeriod(ACTtoPRE) CommandPeriod(PREtoACT) ActiveCommandToRead/WriteCommandDelayTime CommandPeriod(ACT[0]toACT[1]) InputDataToPrecharge CASLatency=3 Command Delay time CAS Latency=2 InputDataToActive/Refresh CASLatency=3 Command Delay time (DuringAuto-Precharge) CAS Latency=2 TransitionTime ExittoSelf-RefreshtoActiveTime RefreshCycleTime(4096) Ta 70oC Com., Ind., A1, A2 Ta 85oC Ind., A1, A2 Ta > 85oC A2 Parameter ClockCycleTime Min. Max. 5 -- 7.5 -- -- 5 -- 6 2 -- 2 -- 2.5 -- 2.5 -- 0 -- -- 5 -- 6 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1CLK+3 -- 1.5 -- 0.8 -- 55 -- 40 100,000 15 -- 15 -- 10 -- 2CLK -- 2CLK 2CLK+trp 2CLK+trp 0.3 60 -- -- -- -- -- -- 1.2 -- 64 -- -- -6 Min. Max. 6 -- 7.5 -- -- 5.4 -- 6 2 -- 2 -- 2.5 -- 2.5 -- 0 -- -- 5.4 -- 6 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1CLK+3 -- 1.5 -- 0.8 -- 60 -- 42 100,000 18 -- 18 -- 12 -- 2CLK -- 2CLK 2CLK+trp 2CLK+trp 0.3 66 -- -- -- -- -- -- 1.2 -- 64 64 -- -7 Min. Max. 7 -- 7.5 -- -- 5.4 -- 6 2.5 -- 2.5 -- 2.7 -- 2.7 -- 0 -- -- 5.4 -- 6 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1CLK+3 -- 1.5 -- 0.8 -- 63 -- 42 100,000 20 -- 20 -- 14 -- 2CLK -- 2CLK 2CLK+trp 2CLK+trp 0.3 70 -- -- -- -- -- -- 1.2 -- 64 64 16 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
Notes: 1. Whenpowerisfirstapplied,memoryoperationshouldbestarted200safterVddandVddq reach their stipulated voltages. Also notethatthepower-onsequencemustbeexecutedbeforestartingmemoryoperation. 2. measured with tt =1ns. 3. Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih (min.)andVil (max.). 4. Accesstimeismeasuredat1.4Vwiththeloadshowninthefigurebelow. 5. Thetimethz (max.)isdefinedasthetimerequiredfortheoutputvoltagetotransitionby200mVfromVoh (min.)orVol(max.) when the output is in the high impedance state. 6. If clock rising time is longer than 1ns, tr/2 - 0.5ns should be added to the parameter.
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OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL -- -- tccd tcked tped tdqd tdqm tdqz tdwd tdal tdpl tbdl tcdl trdl tmrd troh PARAMETER ClockCycleTime CL=3 CL=2 OperatingFrequency CL=3 CL=2 READ/WRITEcommandtoREAD/WRITEcommand CKEtoclockdisableorpower-downentrymode CKEtoclockenableorpower-downexitsetupmode DQM to input data delay DQMtodatamaskduringWRITEs DQMtodatahigh-impedanceduringREADs WRITEcommandtoinputdatadelay Data-intoACTIVEcommand Data-intoPRECHARGEcommand Lastdata-intoburstSTOPcommand Lastdata-intonewREAD/WRITEcommand Lastdata-intoPRECHARGEcommand LOADMODEREGISTERcommand toACTIVEorREFRESHcommand Data-outtohigh-impedancefrom PRECHARGEcommand CL=3 CL=2 CL=3 CL=3 -5 5 7.5 200 133 1 1 1 0 0 2 0 5 4 2 1 1 2 2 3 2 -6 6 7.5 166 133 1 1 1 0 0 2 0 5 5 2 1 1 2 2 3 2 -7 7 7.5 143 133 1 1 1 0 0 2 0 5 5 2 1 1 2 2 3 2 UNITS ns ns MHz MH cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle

AC TEST CONDITIONS (Input/OutputReferenceLevel:1.4V) Input Load
tCK tCHI
3.0V
Output Load
tCL
CLK 1.4V
0V 3.0V
50 I/O
tCS tCH
+1.4V 50 pF
INPUT 1.4V
0V
tOH OUTPUT
1.4V
tAC
1.4V
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FUNCTIONAL DESCRIPTION
The64MbSDRAMs(1Megx16x4banks)arequad-bank DRAMswhichoperateat3.3Vandincludeasynchronous interface (all signals are registered on the positive edge of theclocksignal,CLK).Eachofthe16,777,216-bitbanksis organized as 4,096 rows by 256 columns by 16 bits. ReadandwriteaccessestotheSDRAMareburstoriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVEcommandwhichisthenfollowedbyaREADorWRITE command.Theaddressbitsregisteredcoincidentwiththe ACTIVEcommandareusedtoselectthebankandrowto be accessed (BA0andBA1selectthebank,A0-A11selectthe row).Theaddressbits(A0-A7) registered coincident with the READorWRITEcommandareusedtoselectthestarting column location for the burst access. Prior to normal operation, the SDRAM must be initialized.Thefollowingsectionsprovidedetailedinformation covering device initialization, register definition, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. The64MbSDRAMisinitializedafterthepowerisapplied toVddandVddq (simultaneously), and the clock is stable withDQMHighandCKEHigh. A 100s delay is required prior to issuing any command other than a COMMANDINHIBIT or a NOP.TheCOMMAND INHIBITorNOPmaybeappliedduringthe100speriodand continue should at least through the end of the period. WithatleastoneCOMMANDINHIBITorNOPcommand havingbeenapplied,aPRECHARGEcommandshould be applied once the 100s delay has been satisfied. All banksmustbeprecharged.Thiswillleaveallbanksin an idle state, afterwhichatleasttwoAUTOREFRESH cycles must be performed. After the AUTOREFRESH cycles are complete, the SDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknownstate.AftertheLoadModeRegistercommand, at least one NOP command must be asserted prior to any command.
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REGISTER DEFINITION Mode Register
The mode register is used to define the specific mode ofoperationoftheSDRAM.Thisdefinitionincludesthe selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODEREGISTERDEFINITION. ThemoderegisterisprogrammedviatheLOADMODE REGISTERcommandandwillretainthestoredinformation until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4- M6 specify the CAS latency, M7 and M8 specify the operating mode,M9specifiestheWRITEburstmode,andM10and M11 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiatingthesubsequentoperation.Violatingeitherofthese requirements will result in unspecified operation.
MODE REGISTER DEFINITION
A11 A10
(1)
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus Mode Register (Mx)
Reserved
Burst Length M2 0 0 0 0 1 1 1 1 Burst Type M3 0 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 Operating Mode M8 M7 00 ---- M6-M0 Defined -- Mode Standard Operation All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Type Sequential Interleaved M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 M3=0 1 2 4 8 Reserved Reserved Reserved Full Page M3=1 1 2 4 8 Reserved Reserved Reserved Reserved
Write Burst Mode M9 0 1 Mode Programmed Burst Length Single Location Access
1. To ensure compatibility with future devices, should program M11, M10 = "0, 0"
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Burst Length
ReadandwriteaccessestotheSDRAMareburstoriented, with the burst length being programmable, as shown in MODEREGISTERDEFINITION.Theburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcan beaccessedforagivenREADorWRITEcommand.Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type.The full-page burstisusedinconjunctionwiththeBURSTTERMINATE command to generate arbitrary burst lengths. Reservedstatesshouldnotbeused,asunknownoperation or incompatibility with future versions may result. WhenaREADorWRITEcommandisissued,ablockof columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary isreached.TheblockisuniquelyselectedbyA1-A7(x16) whentheburstlengthissettotwo;byA2-A7(x16)when theburstlengthissettofour;andbyA3-A7(x16)whenthe burstlengthissettoeight.Theremaining(leastsignificant) address bit(s) is (are) used to select the starting location withintheblock.Full-pageburstswrapwithinthepageif the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be eithersequentialorinterleaved;thisisreferredtoasthe burst type and is selected via bit M3. Theorderingofaccesseswithinaburstisdeterminedby the burst length, the burst type and the starting column address,asshowninBURSTDEFINITIONtable.
BURST DEFINITION
Burst Length 2 Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n=A0-A7 (location 0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn,Cn+1,Cn+2 Cn+3,Cn+4... ...Cn - 1, Cn... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NotSupported
4
8
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CAS Latency
The CAS latency is the delay, in clock cycles, between the registrationofaREADcommandandtheavailabilityof thefirstpieceofoutputdata.Thelatencycanbesettotwoor three clocks. IfaREADcommandisregisteredatclockedgen,and the latency is m clocks, the data will be available by clock edge n + m.TheDQswillstartdrivingasaresultofthe clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m.Forexample,assumingthattheclock cycle time is such that all relevant access times are met, ifaREADcommandisregisteredatT0andthelatency is programmed to two clocks, the DQs will start driving afterT1andthedatawillbevalidbyT2,asshowninCAS Latencydiagrams.TheAllowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reservedstatesshouldnotbeusedasunknownoperation or incompatibility with future versions may result.
Operating Mode
ThenormaloperatingmodeisselectedbysettingM7andM8 tozero;theothercombinationsofvaluesforM7andM8are reservedforfutureuseand/ortestmodes.Theprogrammed burstlengthappliestobothREADandWRITEbursts. Testmodesandreservedstatesshouldnotbeusedbecause unknown operation or incompatibility with future versions may result.
Write Burst Mode
WhenM9=0,theburstlengthprogrammedviaM0-M2 appliestobothREADandWRITEbursts;whenM9=1, theprogrammedburstlengthappliestoREADbursts,but write accesses are single-location (nonburst) accesses.
CAS Latency Allowable Operating Frequency (MHz)
Speed 5 6 7 CAS Latency = 2 133 133 133 CAS Latency = 3 200 166 143
CAS Latency
T0 CLK T1 T2 T3
COMMAND DQ
READ
NOP tAC
NOP DOUT
tLZ CAS Latency - 2
tOH
T0 CLK
T1
T2
T3
T4
COMMAND DQ
READ
NOP
NOP tAC
NOP DOUT
tLZ CAS Latency - 3
tOH DON'T CARE UNDEFINED
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OPERATION BANK/ROW ACTIVATION
Before any READ orWRITE commands can be issued toabankwithintheSDRAM,arowinthatbankmustbe "opened."ThisisaccomplishedviatheACTIVEcommand, which selects both the bank and the row to be activated (see ActivatingSpecificRowWithinSpecificBank). After opening a row (issuinganACTIVEcommand),aREAD orWRITEcommandmaybeissuedtothatrow,subjectto the trcd specification. Minimum trcd should be divided by theclockperiodandroundeduptothenextwholenumber to determine the earliest clock edge after the ACTIVE commandonwhichaREADorWRITEcommandcanbe entered.Forexample,atrcd specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to3.Thisisreflectedinthefollowingexample,whichcoversanycasewhere2<[trcd(MIN)/tck] 3.(Thesame procedure is used to convert other specification limits from time units to clock cycles). AsubsequentACTIVEcommandtoadifferentrowinthe same bank can only be issued after the previous active rowhasbeen"closed"(precharged).Theminimumtime interval between successive ACTIVE commands to the same bank is defined by trc. AsubsequentACTIVEcommandtoanotherbankcanbe issued while the first bank is being accessed, which results inareductionoftotalrow-accessoverhead.Theminimum timeintervalbetweensuccessiveACTIVEcommandsto different banks is defined by trrd.
Activating Specific Row Within Specific Bank
CLK CKE CS RAS CAS WE A0-A11 BA0, BA1 ROW ADDRESS BANK ADDRESS HIGH - Z
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] 3
T0 CLK
T1
T2
T3
T4
COMMAND
ACTIVE
NOP tRCD
NOP
READ or WRITE
DON'T CARE
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READS
READ bursts are initiated with a READ command, as shownintheREADCOMMANDdiagram. Thestartingcolumnandbankaddressesareprovidedwith theREADcommand,andautoprechargeiseitherenabledor disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericREADcommandsusedinthefollowing illustrations, auto precharge is disabled. DuringREADbursts,thevaliddata-outelementfromthe starting column address will be available following the CASlatencyaftertheREADcommand.Eachsubsequent data-outelementwillbevalidbythenextpositiveclock edge.The CAS Latency diagram shows general timing for each possible CAS latency setting. Uponcompletionofaburst,assumingnoothercommands havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) DatafromanyREADburstmaybetruncatedwithasubsequentREADcommand,anddatafromafixed-length READburstmaybeimmediatelyfollowedbydatafroma READcommand.Ineithercase,acontinuousflowofdata canbemaintained.Thefirstdataelementfromthenew burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. ThenewREADcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.Thisis showninConsecutiveREADBurstsforCASlatenciesof twoandthree;dataelementn + 3 is either the last of a burstoffourorthelastdesiredofalongerburst.The64Mb SDRAMusesapipelinedarchitectureandthereforedoes not require the 2n rule associated with a prefetch architecture.AREADcommandcanbeinitiatedonanyclockcycle followingapreviousREADcommand.Full-speedrandom read accesses can be performed to the same bank, as showninRandomREADAccesses,oreachsubsequent READmaybeperformedtoadifferentbank. DatafromanyREADburstmaybetruncatedwithasubsequent WRITE command, and data from a fixed-length READburstmaybeimmediatelyfollowedbydatafroma WRITEcommand(subjecttobusturnaroundlimitations). TheWRITEburstmaybeinitiatedontheclockedgeimmediately following the last (or last desired) data element fromtheREADburst,providedthatI/Ocontentioncanbe avoided. In a given system design, there may be a possibilitythatthedevicedrivingtheinputdatawillgoLow-Z beforetheSDRAMDQsgoHigh-Z.Inthiscase,atleast a single-cycle delay should occur between the last read dataandtheWRITEcommand. 22
READ COMMAND
CLK CKE CS RAS CAS WE A0-A7 A8, A9, A11
AUTO PRECHARGE COLUMN ADDRESS HIGH-Z
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
TheDQMinputisusedtoavoidI/Ocontention,asshown inFiguresRW1andRW2.TheDQMsignalmustbeasserted (HIGH) at least three clocks prior to theWRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once theWRITE commandisregistered,theDQswillgoHigh-Z(orremain High-Z),regardlessofthestateoftheDQMsignal,provided theDQMwasactiveontheclockjustpriortotheWRITE commandthattruncatedtheREADcommand.Ifnot,the secondWRITEwillbeaninvalidWRITE.Forexample,if DQMwasLOWduringT4inFigureRW2,thentheWRITEs atT5andT7wouldbevalid,whiletheWRITEatT6would be invalid. TheDQMsignalmustbede-assertedpriortotheWRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Afixed-lengthREADburstmaybefollowedby,ortruncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst maybetruncatedwithaPRECHARGEcommandtothe samebank.ThePRECHARGEcommandshouldbeissued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minusone.ThisisshownintheREADtoPRECHARGE
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diagramforeachpossibleCASlatency;dataelementn + 3 is either the last of a burst of four or the last desired of alongerburst.FollowingthePRECHARGEcommand,a subsequent command to the same bank cannot be issued until trpismet.Notethatpartoftherowprechargetimeis hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burstwithautoprecharge.ThedisadvantageofthePRECHARGEcommandisthatitrequiresthatthecommand and address buses be available at the appropriate time to issuethecommand;theadvantageofthePRECHARGE commandisthatitcanbeusedtotruncatefixed-length or full-page bursts. Full-pageREADburstscanbetruncatedwiththeBURST TERMINATE command, and fixed-length READ bursts maybetruncatedwithaBURSTTERMINATEcommand, providedthatautoprechargewasnotactivated.TheBURST TERMINATEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.Thisis shownintheREADBurstTerminationdiagramforeach possibleCASlatency;dataelementn + 3 is the last desired data element of a longer burst.
CAS Latency
T0 CLK T1 T2 T3
COMMAND DQ
READ
NOP tAC
NOP DOUT
tLZ CAS Latency - 2
tOH
T0 CLK
T1
T2
T3
T4
COMMAND DQ
READ
NOP
NOP tAC
NOP DOUT
tLZ CAS Latency - 3
tOH DON'T CARE UNDEFINED
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Consecutive READ Bursts
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
READ x =1 cycle
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP x = 2 cycles
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b DON'T CARE
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Random READ Accesses
T0 CLK
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ CAS Latency - 2
DOUT n
DOUT b
DOUT m
DOUT x DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ CAS Latency - 3
DOUT n
DOUT b
DOUT m
DOUT x DON'T CARE
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RW1 - READ to WRITE
T0 CLK
T1
T2
T3
T4
T5
T6
DQM
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
tHZ DQ CAS Latency - 2 DON'T CARE DOUT n
DOUT n+1 DOUT n+2
DIN b tDS
RW2 - READ to WRITE
T0 CLK
T1
T2
T3
T4
T5
DQM
COMMAND
READ
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 3
tHZ DOUT n
DIN b tDS DON'T CARE
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IS42S16400F IS45S16400F
READ to PRECHARGE
T0 CLK
T1
T2
T3
T4
T5 tRP
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
x = 1 cycle
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
T0 CLK
T1
T2
T3
T4
T5 tRP
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP x = 2 cycles
NOP
ACTIVE
ADDRESS
BANK, COL n
BANK, COL b
BANK a, ROW
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
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READ Burst Termination
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP
NOP
x = 1 cycle
ADDRESS
BANK a, COL n
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP x = 2 cycles
NOP
NOP
ADDRESS
BANK, COL n
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
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IS42S16400F IS45S16400F
WRITEs
WRITEburstsareinitiatedwithaWRITEcommand,as showninWRITECommanddiagram. AnexampleisshowninWRITEtoWRITEdiagram.Data n + 1 is either the last of a burst of two or the last desired of a longer burst.The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associatedwithaprefetcharchitecture.AWRITEcommand can be initiated on any clock cycle following a previous WRITEcommand.Full-speedrandomwriteaccesseswithin a page can be performed to the same bank, as shown in RandomWRITECycles,oreachsubsequentWRITEmay be performed to a different bank. DataforanyWRITEburstmaybetruncatedwithasubsequentREADcommand,anddataforafixed-lengthWRITE burstmaybeimmediatelyfollowedbyasubsequentREAD command.OncetheREADcommandisregistered,the datainputswillbeignored,andWRITEswillnotbeexecuted.AnexampleisshowninWRITEtoREAD.Datan + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-pageWRITE burst may be truncated with a PRECHARGE command to the same bank.The PRECHARGEcommandshouldbeissuedtwr after the clock edge at which the last desired input data element isregistered.Theautoprechargemoderequiresatwr of at least one clock plus time, regardless of frequency. In addition,whentruncatingaWRITEburst,theDQMsignal must be used to mask input data for the clock edge prior to,andtheclockedgecoincidentwith,thePRECHARGE command.AnexampleisshownintheWRITEtoPRECHARGEdiagram.Datan+1 is either the last of a burst oftwoorthelastdesiredofalongerburst.Followingthe PRECHARGEcommand,asubsequentcommandtothe same bank cannot be issued until trp is met. Inthecaseofafixed-lengthburstbeingexecutedtocompletion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that wouldresultfromthesamefixed-lengthburstwithauto precharge.ThedisadvantageofthePRECHARGE command is that it requires that the command and address buses be availableattheappropriatetimetoissuethecommand;the advantageofthePRECHARGEcommandisthatitcanbe usedtotruncatefixed-lengthorfull-pagebursts. Fixed-lengthorfull-pageWRITEburstscanbetruncated withtheBURSTTERMINATEcommand.WhentruncatingaWRITEburst,theinputdataappliedcoincidentwith theBURSTTERMINATEcommandwillbeignored.The lastdatawritten(providedthatDQMisLOWatthattime) will be the input data applied one clock previous to the BURSTTERMINATEcommand.ThisisshowninWRITE BurstTermination,wheredatan is the last desired data element of a longer burst. 29
WRITE Command
CLK CKE CS RAS CAS WE A0-A7 A8, A9, A11
AUTO PRECHARGE COLUMN ADDRESS HIGH - Z
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
Thestartingcolumnandbankaddressesareprovidedwith theWRITEcommand,andautoprechargeiseitherenabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericWRITEcommandsusedinthe following illustrations, auto precharge is disabled. DuringWRITEbursts,thefirstvaliddata-in element will be registered coincident with the WRITEcommand. Subsequent data elements will be registered on each successive positiveclockedge.Uponcompletionofafixed-lengthburst, assuming no other commands have been initiated, the DQswillremainHigh-Zandanyadditionalinputdatawill beignored(seeWRITEBurst).Afull-pageburstwillcontinue until terminated. (At the end of the page, it will wrap to column 0 and continue.) DataforanyWRITEburstmaybetruncatedwithasubsequentWRITEcommand,anddataforafixed-lengthWRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on anyclockfollowingthepreviousWRITEcommand,andthe data provided coincident with the new command applies to the new command. Integrated Silicon Solution, Inc. -- www.issi.com
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WRITE Burst
T0 CLK T1 T2 T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK, COL n
DQ
DIN n
DIN n+1 DON'T CARE
WRITE to WRITE
T0 CLK T1 T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DIN b DON'T CARE
Random WRITE Cycles
T0 CLK T1 T2 T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ
DIN n
DIN b
DIN m
DIN x
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WRITE to READ
T0 CLK
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1 CAS Latency - 2
DOUT b
DOUT b+1 DON'T CARE
WP1 - WRITE to PRECHARGE
T0 CLK T1 T2 T3 T4 T5 T6
DQM tRP COMMAND WRITE NOP
PRECHARGE
NOP
ACTIVE
NOP
NOP
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
tWR DQ DIN n DIN n+1
CAS Latency - 2
DON'T CARE
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WP2 - WRITE to PRECHARGE
T0 CLK T1 T2 T3 T4 T5 T6
DQM tRP COMMAND WRITE NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
tWR DQ DIN n DIN n+1 CAS Latency - 3 DON'T CARE
WRITE Burst Termination
T0 CLK T1 T2
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK, COL n
(ADDRESS)
DQ
DIN n
(DATA) DON'T CARE
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IS42S16400F IS45S16400F
PRECHARGE
ThePRECHARGEcommand(seefigure)isusedtodeactivate the open row in a particular bank or the open row in allbanks.Thebank(s)willbeavailableforasubsequentrow access some specified time (trp)afterthePRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only onebankistobeprecharged,inputsBA0,BA1selectthe bank.Whenallbanksaretobeprecharged,inputsBA0, BA1aretreatedas"Don'tCare."Onceabankhasbeen precharged, it is in the idle state and must be activated priortoanyREADorWRITEcommandsbeingissuedto that bank.
PRECHARGE Command
CLK CKE CS RAS CAS WE
HIGH - Z
POWER-DOWN
Power-downoccursifCKEisregisteredLOWcoincident withaNOPorCOMMANDINHIBITwhennoaccesses are in progress. If power-down occurs when all banks are idle,thismodeisreferredtoasprechargepower-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers,excludingCKE,formaximumpowersavingswhile instandby.Thedevicemaynotremaininthepower-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. Thepower-downstateisexitedbyregisteringaNOPor COMMANDINHIBITandCKEHIGHatthedesiredclock edge (meeting tcks). See figure below.
A0-A9, A11
ALL BANKS
A10
BANK SELECT
BA0, BA1
BANK ADDRESS
POWER-DOWN
CLK tCKS CKE tCKS
COMMAND
NOP Input buffers gated off
NOP
ACTIVE tRCD tRAS tRC DON'T CARE
All banks idle
Enter power-down mode
Exit power-down mode
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IS42S16400F IS45S16400F
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst isinprogressandCKEisregisteredLOW.Intheclock suspendmode,theinternalclockisdeactivated,"freezing" the synchronous logic. ForeachpositiveclockedgeonwhichCKEissampled LOW,thenextinternalpositiveclockedgeissuspended. Any command or data present on the input pins at the time ofasuspendedinternalclockedgeisignored;anydata presentontheDQpinsremainsdriven;andburstcounters are not incremented, as long as the clock is suspended. (Seefollowingexamples.) ClocksuspendmodeisexitedbyregisteringCKEHIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5
CKE INTERNAL CLOCK COMMAND NOP WRITE NOP NOP
ADDRESS
BANK a, COL n
DQ
DIN n
DIN n+1
DIN n+2 DON'T CARE
Clock Suspend During READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
CKE INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP
ADDRESS
BANK a, COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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BURST READ/SINGLE WRITE
Theburstread/singlewritemodeisenteredbyprogramming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of theprogrammedburstlength.READcommandsaccess columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 =0). SDRAMssupportCONCURRENTAUTOPRECHARGE. FourcaseswhereCONCURRENTAUTOPRECHARGE occurs are defined below.
READ with Auto Precharge
1.InterruptedbyaREAD(withorwithoutautoprecharge): AREADtobankmwillinterruptaREADonbankn, CAS latency later.The PRECHARGE to bank n will beginwhentheREADtobankmisregistered. 2.InterruptedbyaWRITE(withorwithoutautoprecharge): AWRITEtobankmwillinterruptaREADonbankn when registered. DQM should be used two clocks prior totheWRITEcommandtopreventbuscontention.The PRECHARGEtobanknwillbeginwhentheWRITEto bank m is registered.
CONCURRENT AUTO PRECHARGE
Anaccesscommand(READorWRITE)toanotherbank while an access command with auto precharge enabled is executingisnotallowedbySDRAMs,unlesstheSDRAM supports CONCURRENT AUTO PRECHARGE. ISSI
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0 CLK COMMAND BANK n NOP
READ - AP BANK n
T1
T2
T3
T4
T5
T6
T7
NOP
READ - AP BANK m
NOP
NOP
NOP
NOP
Page Active
READ with Burst of 4
Interrupt Burst, Precharge tRP - BANK n
Idle tRP - BANK m Precharge
Internal States
BANK m ADDRESS DQ CAS Latency - 3 (BANK n)
BANK n, COL a
Page Active
READ with Burst of 4
BANK m, COL b
DOUT a
DOUT a+1
DOUT b
DOUT b+1 DON'T CARE
CAS Latency - 3 (BANK m)
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0 CLK COMMAND BANK n
WRITE - AP BANK n
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
WRITE - AP BANK m
NOP
NOP
NOP Idle tRP - BANK m Write-Back
READ with Burst of 4 Page Active Page Active
BANK n, COL a BANK m, COL b
Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4
Internal States
BANK m ADDRESS DQM DQ
DOUT a CAS Latency - 3 (BANK n)
DIN b
DIN b+1
DIN b+2
DIN b+3 DON'T CARE
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IS42S16400F IS45S16400F
WRITE with Auto Precharge
3.InterruptedbyaREAD(withorwithoutautoprecharge): AREADtobankmwillinterruptaWRITEonbankn when registered, with the data-out appearing CAS latency later.ThePRECHARGEtobanknwillbeginaftertwr is met, where twrbeginswhentheREADtobankmis registered.ThelastvalidWRITE to bank n will be data-in registeredoneclockpriortotheREADtobankm. 4.InterruptedbyaWRITE(withorwithoutautoprecharge): AWRITE to bank m will interrupt a WRITE on bank n when registered.ThePRECHARGEtobanknwillbeginafter twr is met, where twrbeginswhentheWRITEtobank misregistered.ThelastvaliddataWRITEtobankn willbedataregisteredoneclockpriortoaWRITEto bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0 CLK T1 T2 T3 T4 T5 T6 T7
COMMAND
NOP
WRITE - AP BANK n
NOP
READ - AP BANK m
NOP
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m Precharge
Internal States
BANK m Page Active
BANK n, COL a BANK m, COL b
READ with Burst of 4
ADDRESS
DQ
DIN a
DIN a+1 CAS Latency - 3 (BANK m)
DOUT b
DOUT b+1 DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0 CLK T1 T2 T3 T4 T5 T6 T7
COMMAND
NOP
WRITE - AP BANK n
NOP
NOP
WRITE - AP BANK m
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m Write-Back
Internal States
BANK m Page Active
BANK n, COL a BANK m, COL b
WRITE with Burst of 4
ADDRESS
DQ
DIN a
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3 DON'T CARE
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INITIALIzE AND LOAD MODE REGISTER(1)
T0 CLK
tCK
T1
Tn+1 tCH
To+1 tCL
Tp+1
Tp+2
Tp+3
tCKS tCKH CKE tCMH tCMS COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ T Power-up: VCC and CLK stable T = 100s Min. tRP Precharge all banks tRC AUTO REFRESH tRC AUTO REFRESH tMRD Program MODE REGISTER (2, 3, 4) DON'T CARE ALL BANKS BANK CODE tAS tAH CODE ROW ROW NOP tCMH tCMS PRECHARGE tCMH tCMS
AUTO REFRESH
NOP
AUTO REFRESH
NOP
Load MODE REGISTER
NOP
ACTIVE
At least 2 Auto-Refresh Commands
Notes: 1. If CSisHighatclockHightime,allcommandsappliedareNOP. 2.TheModeregistermaybeloadedpriortotheAuto-Refreshcyclesifdesired. 3.JEDECandPC100specifythreeclocks. 4.OutputsareguaranteedHigh-Zafterthecommandisissued.
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IS42S16400F IS45S16400F
POWER-DOWN MODE CYCLE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK BANK ROW ROW PRECHARGE NOP NOP NOP ACTIVE tCK T1 tCL tCKS T2 tCH tCKS Tn+1 Tn+2
DQ High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode Input buffers gated off while in power-down mode All banks idle
Exit power-down mode
DON'T CARE
CASlatency=2,3
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IS42S16400F IS45S16400F
CLOCK SUSPEND MODE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 tAS tAH BA0, BA1 BANK tAC DQ tLZ DOUT m tOH DON'T CARE UNDEFINED tAC tHZ DOUT m+1 BANK tDS tDH DOUT e DOUT e+1 COLUMN m(2) tAS tAH COLUMN n(2) READ NOP tCMS tCMH NOP NOP NOP NOP WRITE NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
tCL
tCH
tCKS tCKH
Notes: 1. CASlatency=3,burstlength=2 2. A8, A9, and A11="Don'tCare"
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Rev. F 11/09/09
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IS42S16400F IS45S16400F
AUTO-REFRESH CYCLE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ BANK(s) tAS tAH High-Z tRP tRC tRC DON'T CARE
CASlatency=2,3
tCK
T1
tCL
T2
tCH
Tn+1
To+1
PRECHARGE
NOP
Auto Refresh
NOP
Auto Refresh
NOP
ACTIVE
ROW ROW BANK
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Rev. F 11/09/09
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SELF-REFRESH CYCLE
T0 CLK tCK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK tXSR CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE PRECHARGE NOP
Auto Refresh
T1 tCH tCL
T2 tCKS
Tn+1
To+1
To+2
tRAS tCKS NOP NOP
Auto Refresh
DQ High-Z Precharge all active banks
tRP Enter self refresh mode
Note: 1.Self-RefreshModeisnotsupportedforA2gradewithTa > 85oC.
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Rev. F 11/09/09
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READ WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD tRAS tRC tLZ CAS Latency ROW tAS tAH ROW tAS tAH BANK COLUMN m(2) ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tAC tAC DOUT m tOH tAC DOUT m+1 tOH SINGLE BANK BANK tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
Notes: 1. CASlatency=2,burstlength=4 2. A8, A9, and A11="Don'tCare"
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Rev. F 11/09/09
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READ WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD tRAS tRC tLZ CAS Latency ROW tAS tAH ROW tAS tAH BANK BANK tAC tAC DOUT m tOH tAC DOUT m+1 tOH tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP NOP NOP NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
Notes: 1. CASlatency=2,burstlength=4 2. A8, A9, and A11="Don'tCare"
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SINGLE READ WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD tRAS tRC tLZ CAS Latency ROW tAS tAH ROW tAS tAH BANK COLUMN m(2) ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tAC tOH DOUT m tHZ tRP DON'T CARE UNDEFINED SINGLE BANK BANK BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
Notes: 1. CASlatency=2,burstlength=1 2. A8, A9, and A11="Don'tCare"
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SINGLE READ WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD tRAS tRC CAS Latency tRP ROW tAS tAH ROW tAS tAH BANK BANK tAC tOH DOUT m tHZ DON'T CARE UNDEFINED COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK ROW
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
tCMS tCMH
Notes: 1. CASlatency=2,burstlength=1 2. A8, A9, and A11="Don'tCare"
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ALTERNATING BANK READ ACCESSES
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tLZ DQ tAC tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 DON'T CARE CAS Latency - BANK 0 tRCD - BANK 3 COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK 3 tOH DOUT m tAC tOH DOUT m+1 tAC BANK 3 tOH DOUT m+2 tAC tRP - BANK 0 CAS Latency - BANK 3 tOH DOUT m+3 tAC ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW BANK 0 tOH DOUT b tAC tRCD - BANK 0 ROW ACTIVE NOP READ tCMS tCMH NOP ACTIVE NOP READ NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
Notes: 1. CASlatency=2,burstlength=4 2. A8, A9, and A11="Don'tCare"
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READ - FULL-PAGE BURST
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD ROW tAS tAH ROW tAS tAH BANK BANK tAC tLZ CAS Latency DOUT m tAC tAC DOUT m+1 tAC DOUT m+2 tOH tAC DOUT m-1 tOH tAC DOUT m tOH tHZ DOUT m+1 tOH DON'T CARE Full page Full-page burst not self-terminating. completion Use BURST TERMINATE command. UNDEFINED COLUMN m(2)
ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
tCMS tCMH
tOH tOH each row (x4) has 1,024 locations
Notes: 1. CASlatency=2,burstlength=fullpage 2. A8, A9, and A11="Don'tCare"
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READ - DQM OPERATION
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK COLUMN m(2)
ENABLE AUTO PRECHARGE
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
NOP
READ tCMS tCMH
NOP
NOP
NOP
NOP
NOP
NOP
DISABLE AUTO PRECHARGE
BANK tAC tLZ tRCD CAS Latency tOH DOUT m tHZ tLZ tAC tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED
Notes: 1. CASlatency=2,burstlength=4 2. A8, A9, and A11="Don'tCare"
48
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
IS42S16400F IS45S16400F
WRITE - WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK COLUMN m(2) ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tDS DQ tRCD tRAS tRC tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH SINGLE BANK BANK BANK ROW ACTIVE NOP WRITE tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8
DIN m
DIN m+3 tWR(3) tRP
DON'T CARE
Notes: 1. burstlength=4 2. A8, A9, and A11="Don'tCare" 3. tras must not be violated
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
49
IS42S16400F IS45S16400F
WRITE - WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK BANK tDS DQ tRCD tRAS tRC tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK ROW ACTIVE NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP NOP ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 T9
DIN m
DIN m+3 tWR tRP
DON'T CARE
Notes: 1. burstlength=4 2. A8, A9, and A11="Don'tCare"
50
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
IS42S16400F IS45S16400F
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK COLUMN m(2) ROW
ALL BANKS
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
NOP
WRITE tCMS tCMH
NOP(4)
NOP(4)
PRECHARGE
NOP
ACTIVE
NOP
ROW
DISABLE AUTO PRECHARGE SINGLE BANK
BANK tDS tDH
BANK
BANK
DQ tRCD tRAS tRC
DIN m tWR(3) tRP DON'T CARE
Notes: 1. burstlength=1 2. A8, A9, and A11="Don'tCare" 3. tras must not be violated
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
51
IS42S16400F IS45S16400F
SINGLE WRITE - WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK BANK tDS tDH DQ tRCD tRAS tRC DIN m tWR tRP DON'T CARE COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK ROW ACTIVE NOP(3) NOP(3) NOP(3) WRITE tCMS tCMH NOP NOP NOP ACTIVE NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
tCL
tCH
Notes: 1. burstlength=1 2. A8, A9, and A11="Don'tCare"
52
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
IS42S16400F IS45S16400F
ALTERNATING BANK WRITE ACCESS
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tDS DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 tDH tDS tDH DIN m+1 COLUMN m(2) ENABLE AUTO PRECHARGE ROW BANK 1 tDS tDH DIN m+2 tDS tDH BANK 1 tDS tDH DIN b tDS tDH tDS tDH ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW BANK 0 tDS tDH ROW ACTIVE NOP WRITE tCMS tCMH NOP ACTIVE NOP WRITE NOP NOP ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 T9
DIN m
DIN m+3
DIN b+1
DIN b+2
DIN b+3 tRCD - BANK 0 tWR - BANK 1
tWR - BANK 0 tRCD - BANK 1
tRP - BANK 0
DON'T CARE
Notes: 1. burstlength=4 2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
53
IS42S16400F IS45S16400F
WRITE - FULL PAGE BURST
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD ROW tAS tAH ROW tAS tAH BANK BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH tDS tDH tDS tDH DIN m DIN m+3 DIN m-1 DON'T CARE COLUMN m(2)
ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
T1 tCK tCL
T2 tCH
T3
T4
T5
Tn+1
Tn+2
tCMS tCMH
Full page completed
Notes: 1. burstlength=fullpage 2. A8, A9, and A11="Don'tCare"
54
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
IS42S16400F IS45S16400F
WRITE - DQM OPERATION
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ tRCD ROW tAS tAH ROW tAS tAH BANK COLUMN m(2)
ENABLE AUTO PRECHARGE
T1 tCK tCL
T2 tCH
T3
T4
T5
T6
T7
ACTIVE
NOP
WRITE tCMS tCMH
NOP
NOP
NOP
NOP
NOP
DISABLE AUTO PRECHARGE
BANK tDS tDH tDS tDH DIN m+2 tDS tDH DIN m DIN m+3 DON'T CARE
Notes: 1. burstlength=4 2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
55
IS42S16400F IS45S16400F
ORDERING INFORMATION Commercial Range: 0C to 70C
Frequency 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz Speed (ns) 5 5 6 6 7 7 Order Part No. IS42S16400F-5TL IS42S16400F-5BL IS42S16400F-6TL IS42S16400F-6BL IS42S16400F-7TL IS42S16400F-7BL Package 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-ballBGA,SnAgCuballs 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-ballBGA,SnAgCuballs 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-ballBGA,SnAgCuballs
Industrial Range: -40C to 85C
Frequency 166MHz 166MHz 143MHz 143MHz Speed (ns) 6 6 7 7 Order Part No. IS42S16400F-6TLI IS42S16400F-6BLI IS42S16400F-7TLI IS42S16400F-7BLI Package 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-ballBGA,SnAgCuballs 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-ballBGA,SnAgCuballs
Automotive Range (A1): -40C to 85C
Frequency 166MHz 166MHz 166MHz 143MHz 143MHz 143MHz Speed (ns) 6 6 6 7 7 7 Order Part No. IS45S16400F-6TLA1 IS45S16400F-6CTNA1 IS45S16400F-6BLA1 IS45S16400F-7TLA1 IS45S16400F-7CTNA1 IS45S16400F-7BLA1 Package 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-PinTSOPII,Cu leadframe plated withNiPdAu 54-ballBGA,SnAgCuballs 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn 54-PinTSOPII,Cu leadframe plated withNiPdAu 54-ballBGA,SnAgCuballs
Automotive Range (A2): -40C to 105C
Frequency 143MHz 143MHz Speed (ns) 7 7 Order Part No. Package IS45S16400F-7TLA2 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn IS45S16400F-7CTNA2 54-PinTSOPII,Cu leadframe plated withNiPdAu
Notes: 1. Contact ISSI for leaded parts support. 2.Partnumberswith"L"or"N"areleadfree,andRoHScompliant.
56
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
IS42S16400F IS45S16400F
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. F 11/09/09
57
IS42S16400F IS45S16400F
10/17/2007
58 Integrated Silicon Solution, Inc. -- www.issi.com
Package Outline
Rev. F 11/09/09

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